Fuse structure integrated wire bonding on the low k interconnect and method for making the same

ABSTRACT

A structure for using fuse structure integrated wire bonding on the substrate, and relates to methods for making the same are disclosed, in which an Al-fuse has an extra-etching process pattern by fuse-open mask and has been thinned down from Al-fuse thickness. The Al fuse structure integrated Al wire-bonding pad has two kind of thickness under fuse-open and for the other area. This invention makes the fuse easy to blow without suffering any bondability from wire bonding for packaging.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a semiconductordevice, and more particularly to a fuse structure integrated wirebonding on the low k interconnect, and relates to methods for making thesame.

[0003] 2. Description of the Prior Art

[0004] It is the nature of semiconductor physics that as the featuresizes are scaled down, the performance of internal devices in integratedcircuits improves in a compounded fashion. That is, the device speeds aswell as the functional capability improves. The overall circuit speed,however, becomes more dependent upon the propagation speed of thesignals along the interconnections that connect the various devicestogether. With the advent of very and ultra large scale integration(VLSI and ULSI) circuits, it has therefore become even more importantthat the metal conductors that form the interconnections between devicesas well as between circuits in the semiconductor have low resistivitiesfor high signal propagation. Copper is often preferred for its lowresistivities, as well as for resistance to electromigration and stressvoiding properties.

[0005] On the other hand, considerable attention has focused on thereplacement of silicon dioxide with new materials, having a lowerdielectric constant, since both capacitive delays and power consumptiondepend on the dielectric constant of the insulator. Accordingly, circuitperformance enhancement has been sought by combining the copperconductors with low dielectric constant layer (with dielectric constantk less than approximately 4).

[0006] Since low-k material can not sustain laser fusing, fuse of low-kinterconnect is built in Al-pad layer, which is used for wire-bondingpad. As to provide good bondability for wire bonding, the Al-pad layerthickness for this pad is usually as thick as 10000 angstroms, sometimeseven thicker. This is too thick for laser to blow, which diminishes theprocess margin of laser fusing. At some certain degree, it causes fusingfailure.

[0007] For the forgoing reasons, there is a necessity for a structurefor using fuse structure integrated wire bonding on the low kinterconnect, and relates to methods for making the same. This inventionapplies a fuse open pattern in the metal layer.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention is provided to a fusestructure integrated wire bonding on the low k interconnect and relatesto methods for making the same that wire bonding and process margin areprovided both good bondability by laser fusing.

[0009] One object of the present invention is to provide a fusestructure integrated wire bonding on the low k interconnect and relatesto methods for making the same to provide both good bondability for wirebonding and process margin for laser fusing.

[0010] In order to achieve the above objects, the present inventionprovides a fuse structure integrated wire bonding on the low kinterconnect, and relates to methods for making the same. First of all,a first metal layer formed on the first portion of the substrate. Then,a second metal layer formed on the second portion of the substrate,wherein the second metal layer has a concavity thereon. Finally, apassivation layer on the first metal layer, the second metal layer, andthe substrate, wherein the passivation layer has a first opening overthe first metal layer and has a second opening substantially over theconcavity of the second metal layer. The method at least includes thefollowing steps. First of all, a cap layer is formed on the low kinterconnect substrate. The low k interconnect comprises copper. Then,the metal layer is formed on the cap layer. The metal layer comprisesaluminum. Next, a portion of the metal layer is removed to form aconcavity of the metal layer, wherein the second opening align thehollow. The formation of Al-fuse has an extra-etch process patterned byusing fuse-open mask and has been thinned down from Al-fuse thickness.The metal layer is removed to define a pad pattern and a fuse pattern onthe substrate, wherein the fuse pattern have a fuse-open pattern on thetop of the fuse pattern. Next, a conformal passivation layer is formedon the cap layer, the pad pattern, and the fuse pattern. The conformalpassivation layer comprises silicon nitride or silicon oxide. Finally, aportion of the conformal passivation layer is removed to form a firstopening on the top of the pad pattern and a second opening on the top ofthe fuse pattern, wherein the second opening is substantially over theconcavity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by referring to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0012] FIGS. 1-5 are cross-sectional schematic diagrams illustratingfuse structure integrated wire bonding on the low k interconnect inaccordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013] The semiconductor devices of the present invention are applicableto a broad range of semiconductor devices and can be fabricated from avariety of semiconductor materials. While the invention is described interms of a single preferred embodiment, those skilled in the art willrecognize that many steps described below can be altered withoutdeparting from the spirit and scope of the invention.

[0014] Furthermore, there is shown a representative portion of asemiconductor structure of the present invention in enlarged,cross-sections of the two dimensional views at several stages offabrication. The drawings are not necessarily to scale, as the thicknessof the various layers are shown for clarity of illustration and shouldnot be interpreted in a limiting sense. Accordingly, these regions willhave dimensions, including length, width and depth, when fabricated inan actual device.

[0015] This invention declares a bi-level Al-fuse for the Cu/low-kinterconnect, which provides both good bondability for wire bonding andprocess margin for laser fusing. The formation of Al-fuse has anextra-etch process patterned by using fuse-open mask and has beenthinned down from typically 10000 angstroms, Al-pad thickness, to 5000angstroms, normal Al-fuse thickness. The Al fuse structure integrated Alwire-bonding pad has two kind of thickness, 5000 angstroms underfuse-open and 10000 angstroms for the other area. This makes the fuseeasy to blow without suffering any bondability from wire-bonding forpackaging.

[0016] The embodiment of the present invention is depicted in the FIGS.1-5, which show a cross-section of fuse structure integrated wirebonding on the low k interconnect in accordance with the presentinvention.

[0017] Referring to FIG. 1, a conductor having a low resistivity, suchas copper, is provided in a low k interconnect substrate 100. Sincecopper has higher resistance to electromigration and lower electricalresistivity, it is a kind of preferred material for interconnect wiring.Then, a cap layer 102 is formed on the low k interconnect substrate 100,wherein the cap layer 102 has some openings (three in this embodiment)to expose the substrate 100. The cap layer 102 comprises oxide. The caplayer 102 can protect conductor from being harmed and provide aresistance of copper outward diffusion. Consequently, the cap layer 102is acted as a passivation layer. Then, a metal layer 104 is formed onthe cap layer 102. The metal layer 104 comprises aluminum. The metallayer 104 is formed with a thickness between 10000 angstroms and 20000angstroms. In the embodiment, thickness of this layer 104 is preferableless than angstroms. The metal layer 104 is deposited by using achemical vapor deposition (CVD), low pressure chemical vapor deposition(LPCVD), or plasma enhance chemical vapor deposition (PECVD) method. Inthe embodiment, deposit of this layer 104 is preferable method.

[0018] Referring to FIG. 2, a first photoresist layer is formed (notshow in the figure) as a first mask over portions of the metal layer104. The first photoresist layer may be spin-coated on the metal layer104, and patterned to form a fuse-open through exposure and development.The mask isn't reworked because the mask of Al-fuse is formed afterprocess. Once developed, the fuse-open will serve as a second mask todefine the etching locations over the metal layer 104. However, aportion of the metal layer 104 is etched with fuse-open mask to form aconcavity of the metal layer 104 to define a fuse-open pattern 105,wherein the formation of Al-fuse has an extra-etch process patterned byusing fuse-open mask. The fuse-open pattern 105 is formed with athickness of about 5000 angstroms in the metal layer 104. The stepwiseprofile of the metal layer 104 is different from the thickness ofitself. The metal layer 104 is removed by using anisotropical etch. Theanisotropical etch provides an opening in the second metal layer 104,and said opening keeping at a predetermined distance for the cap layer102.

[0019] Referring to FIG. 3, a second photoresist layer (not show in thefigure) is deposited on the metal layer 104. The second photoresistlayer has a few openings (three in this embodiment) by usingconventional lithographic technology, wherein the metal layer 104 isremoved by using the second photoresist layer as a mask. The metal layer104 is removed to define a pad pattern 106 and a fuse pattern 108 in themetal layer 104, wherein the fuse pattern 108 having the fuse-openpattern 105. The metal layer 104 is etched by using an anisotropicaletch. The anisotropical etch provides an opening in the second metallayer 104, and said opening keeping at a predetermined distance for thecap layer 102.

[0020] Referring to FIG. 4, a conformal passivation layer 110 is formedon the cap layer 102, the pad pattern 106, and the fuse pattern 108. Theconformal passivation layer 110 comprises silicon nitride and/or siliconoxide. The conformal passivation layer 110 is formed with a thicknessbetween 8000 angstroms and 15000 angstroms. In the embodiment, thicknessof this layer is preferable less than angstroms. The conformalpassivation layer 110 is deposited by using a chemical vapor deposition(CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhancechemical vapor deposition (PECVD) method. In the embodiment, deposit ofthis layer 110 is preferable PECVD method. The conformal passivationlayer 110 can protect pad pattern 106 and fuse pattern 108 from beingharmed.

[0021] Referring to FIG. 5, a third photoresist layer (not show in thefigure) is deposited on the conformal passivation layer 110. The thirdphotoresist layer has an opening by using conventional lithographictechnology. Then, a portion of the conformal passivation layer 110 isremoved by using the fuse open as a mask. Then, a portion of theconformal passivation layer is removed to form an opening pattern 112 aon the pad pattern 106 and an opening pattern 112 b on the fuse pattern108. The depth of the opening 102 b in the fuse pattern 108 is deeperthan the depth of the opening 102 a in the pad pattern 106. Theconformal passivation layer 110 is etched by using an anisotropicaletch.

[0022] One of the objects of the present invention is to provide abetter method and structure that the Al-fuse has an extra-etch processpattern by fuse-open mask and has been thinned down from typically 10000angstroms, Al-pad thickness, to 5000 angstroms, normal Al-fusethickness. The Al fuse structure integrated Al wire-bonding pad has twokind of thickness, 5000 angstroms under fuse-open and 10000 angstromsfor the other area. This makes the fuse easy to blow without sufferingany bondability from wire bonding for packaging.

[0023] While this invention has been described with reference toillustrative embodiments, this description is not intended or to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. It is therefore intended that the appended claimsencompass any such modifications or embodiments.

What is claimed is:
 1. A fuse structure integrated wire bonding on asubstrate, said structure comprising: a first metal layer on a firstportion of said substrate; a second metal layer on a second portion ofsaid substrate, wherein said second metal layer has a concavity therein;and a passivation layer on said first metal layer and said second metallayer, wherein said passivation layer has a first opening over saidfirst metal layer and has a second opening substantially over saidconcavity of said second metal layer.
 2. The fuse structure integratedwire bonding on a substrate according to claim 1, wherein said substratecomprises low k interconnect.
 3. The fuse structure integrated wirebonding on a substrate according to claim 1, wherein said first metallayer comprises aluminum.
 4. The fuse structure integrated wire bondingon a substrate according to claim 1, wherein said second metal layercomprises aluminum.
 5. The fuse structure integrated wire bonding on asubstrate according to claim 1, wherein thickness of said concavity isabout 5000 angstroms in said second metal layer.
 6. The fuse structureintegrated wire bonding on a substrate according to claim 1, whereinsaid passivation layer is selected from the group consisting of siliconnitride and silicon oxide.
 7. A method for forming a fuse-open patternon a substrate of the type having a first metal layer formed on a firstportion of said substrate, a second metal layer formed on a secondportion of said substrate, a passivation layer formed on said firstmetal layer and said second metal layer, wherein said passivation layerhas a first opening over said first metal layer and has a second openingover said second metal layer, wherein the improvement comprises:removing a portion of said second metal layer to form a concavity insaid second metal layer, wherein said second opening is substantiallyover said concavity.
 8. The method for forming said fuse-open pattern ona substrate according to claim 7, wherein said substrate comprises low kinterconnect.
 9. The method for forming said fuse-open pattern on asubstrate according to claim 8, wherein said low k interconnectsubstrate comprises copper.
 10. The method for forming said fuse-openpattern on a substrate according to claim 7, wherein said first metallayer comprises aluminum.
 11. The method for forming said fuse-openpattern on a substrate according to claim 7, wherein said second metallayer comprises aluminum.
 12. The method for forming said fuse-openpattern on a substrate according to claim 7, wherein said step ofremoving is anisotropical etch.
 13. The method for forming saidfuse-open pattern on a substrate according to claim 12, wherein saidanisotropical etch provides an opening in said second metal layer, andsaid opening keeping at a predetermined distance for said cap layer. 14.The method for forming said fuse-open pattern on a substrate accordingto claim 7, wherein said concavity is formed with a thickness of about5000 angstroms in said metal layer.
 15. The method for forming saidfuse-open pattern on a substrate according to claim 7, wherein saidpassivation layer is selected from the group consisting of siliconnitride and silicon oxide.
 16. A method for forming a fuse structureintegrated a wire bonding on a low k interconnect substrate, said methodcomprising: forming a cap layer on said low k interconnect substrate;forming a metal layer on said cap layer; removing a portion of saidmetal layer to form a concavity in said metal layer to define afuse-open pattern; removing a portion of said metal layer to define apad pattern and a fuse pattern on said substrate, wherein said fusepattern have said fuse-open pattern on the top of said fuse pattern;forming a conformal passivation layer on said cap layer, said padpattern, and said fuse pattern; and removing a portion of said conformalpassivation layer to form a first opening in said pad pattern and asecond opening in said fuse pattern, wherein said second opening issubstantially over said concavity.
 17. The method for forming said fusestructure integrated a wire bonding on a low k interconnect substrateaccording to claim 16, wherein said low k interconnect substratecomprises copper.
 18. The method for forming said fuse structureintegrated a wire bonding on a low k interconnect substrate according toclaim 16, wherein said metal layer comprises aluminum.
 19. The methodfor forming said fuse structure integrated a wire bonding on a low kinterconnect substrate according to claim 16, wherein said step ofremoving is anisotropical etch.
 20. The method for forming said fusestructure integrated a wire bonding on a low k interconnect substrateaccording to claim 19, wherein said anisotropical etch provides anopening in said second metal layer, and said opening keeping at apredetermined distance for said cap layer.
 21. The method for formingsaid fuse structure integrated a wire bonding on a low k interconnectsubstrate according to claim 16, wherein said concavity is formed with athickness of about 5000 angstroms in said metal layer.
 22. The methodfor forming said fuse structure integrated a wire bonding on a low kinterconnect substrate according to claim 16, wherein said passivationlayer is selected from the group consisting of silicon nitride andsilicon oxide.
 23. The method for forming said fuse structure integrateda wire bonding on a low k interconnect substrate according to claim 17,wherein said conformal passivation layer is removed by usinganisotropical etch.